The present invention relates to signal converting circuits and, more particularly, to a circuit for converting logic signals represented by certain voltage levels (e.g., for an ECL circuit) into logic signals represented by a different voltage levels (e.g., for a CMOS circuit).
Computer systems today use circuits implemented in different hardware technology. For example, it is not uncommon to find in one computer both CMOS (complementary metal-oxide-semiconductor) and ECL (emitter-coupled logic) circuits. CMOS is often used in very large chips having many transistors (in excess of 100,000) because it requires relatively little power. Other smaller, but faster, chips are normally implemented in ECL.
One problem with having circuits in a single system implemented in different hardware technologies is that the same logic level of the signals from different circuits are represented by different voltages. For example, in an ECL circuit, a logic level "1" or "high" will typically be represented by approximately -0.8 V and a logic level "0" or "low" will typically be represented by approximately -1.6 V. A CMOS circuit, on the other hand, will typically have a logic level "1" represented by ground (0 V) and logic level "0" represented by -5.0 V. It thus becomes necessary to provide a signal converter or interface when the signals from an ECL circuit are provided to an CMOS circuit.
Circuits have been designed for converting ECL logic signals into CMOS logic signals. However, such circuits tend to delay the operation of the system in which they are used. That is, the signals going from the ECL circuit to the CMOS circuit must pass through the converting circuit (normally a plurality of P-channel and N-channel transistors) in order to be converted from one set of voltages to the other, and such conversion adds delay to the overall time for processing the signals.
This problem occurs because prior converter circuits have used MOS transistors at their inputs to sense the voltage level of the signals from the ECL circuit and then provide a signal capable of driving the CMOS buffers or drivers in the converter. These MOS transistors are switched between enabled ("on") and non-enabled ("off") conditions, requiring time to accommodate sufficient voltage swings (e.g., from 0 V to -5 V) across the drain-to-source junction in the transistors. This time adds to the overall delay of the systems in which the converter circuits are used.
There has thus arisen the need for a signal converter circuit which reduces the amount of time needed to convert logic signals represented by one set of voltages into the same logic signals represented by a different set of voltages.